1. Field of the Invention
The present invention relates to an outline compensation circuit.
2. Description of the Prior Art
FIG. 3 shows an example of a conventional outline compensation circuit.
In FIG. 3, reference numerals 1 and 3 denote coefficient multipliers as first coefficient means which reduces the level of an image signal by one half (1/2) and also reverse the polarity thereof. Reference numeral 2 denotes a coefficient multiplier which provides the image signal as an output without any modification or change in the level and the polarity thereof. Reference numeral 4 denotes a delay circuit as first delaying means which delays the signal of the coefficient multiplier 1 by 2.tau. (.tau.=1/4f, f: emphasizing frequency). Reference numeral 5 denotes an adder as first adding means which adds the signal delayed by 2.tau. by the delay circuit 4 to the original image signal of the coefficient multiplier 2. Reference numeral 6 denotes a delay circuit as second delaying means which delays the signal from the adder 5 by 2.tau.. Reference numeral 3 denotes an adder which adds the output signal from the coefficient multiplier 3 to the output signal from the delay circuit 6 to output a second-order differential signal of the original image signal.
The level of the signal shown in FIG. 4A is reduced by one half (1/2) as well as reversed in polarity by the respective coefficient multipliers 1 and 3, but is not modified or changed by the coefficient multiplier 2. The waveform of the output signal of the coefficient multiplier 1 is shown in FIG. 4B. The signal from the coefficient multiplier 1 is delayed by 2.tau. by the delay circuit 4, and then is added to the signal from the coefficient multiplier 2 by the adder 5. The waveform of the output signal from the delay circuit 4 is shown in FIG. 4C, and the waveform of the output signal from the adder 5 is shown in FIG. 4D.
Next, the output signal from the adder 5 is delayed by 2.tau. by the delay circuit 6, and the signal delayed by 2.tau. and the signal from the coefficient multiplier 3 are added to each other by the adder 7. The waveform of the output signal from the delay circuit 6 is shown in FIG. 4E and the waveform of the output signal from the adder 7 is shown in FIG. 4F.
In the conventional outline compensation circuit, there is a drawback in that, because there is a relationship f=1/2.tau. between the emphasizing frequency f and the width .tau. of the outline compensation signal, the outline compensation signal produced when emphasizing the low frequency component, which has the visual effect of emphasizing the outline, widens the width of the outline. In the outline portion having a great difference in the brightness of the image signal, for instance, in an image in which a face of a human being is in the whitish background, an emphasized edge appears unnaturally in the face of the human being, thereby resulting in losing the sharpness of the image.
For example, when emphasizing a 2 MHz component, an outline signal has a width of 250 ns, i.e., an outline edge having a width corresponding to 4 picture cells in terms of CCD at 14.32 MHz is obtained.
In the conventional outline compensation circuit, it is impossible to reduce only the width of the outline signal to one half of the width of the outline signal processed as mentioned above without changing the emphasizing frequency.
Accordingly, a thick edge appears on the screen of a large-sized projector or a large-sized monitor, thereby giving unnatural outline compensation.